module mithani #(parameter CHAI_MIN = 2)(   // doodh patti, cups/day
input  wire classical,
    output reg  my_profile
);  // CpE + EE @ UT Arlington --- Headed towards chip design & EUV lithography

I don't just want to work on a computer. I want to work inside one.

• Undergraduate Research Assistant, Smart Infrastructure and Testing Lab (SITL), CpE + EE @ UTA
• Porting legacy C++ ground-penetrating radar software to Python for Texas Department of Transportation
• Built the lab's equipment monitoring network on Raspberry Pi (private, lab-owned)
• Upgraded lab tooling with custom designed circuitry
• Writing SystemVerilog for an Intel/Altera MAX 10 FPGA

• Meembot: LLM integrated verified Discord bot, 500,000+ members across all servers (source private)
• Compyouters.org: interactive hardware learning site
• CNN object classifier: transfer learning, best coding work of 32 teams
• AI College Advisor: Personalized AI schedule builder

Languages: Python C C++ SystemVerilog/Verilog JavaScript MATLAB
Hardware: Intel MAX 10 FPGA Quartus Prime Raspberry Pi Arduino oscilloscope & bench
Systems: Linux Bash systemd Docker Git
Data & ML: TensorFlow Flask REST SQLite MySQL

Open to Summer 2027 internships: semiconductors, instrumentation, ML.

P.S. tabs > spaces. Period.

endmodule  // tape-out: May 2029