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Project RADP (RISC-V Agentic Design Platform) is an open-source platform that takes a RISC-V processor from a single spec file to RTL, verification, synthesis, FPGA bitstream and shuttle tapeout, using AI agents for the work and deterministic open-source tools for every decision.
- Spec-driven. Everything starts from one versioned
chip.yaml, validated against a JSON Schema. - Gated. Every agent change on a Git branch passes lint, simulation, ISA compliance, lockstep against Spike, formal checks, coverage and timing before a human merges it.
- Inspectable. Every agent step records its inputs, tool calls, diff, gate result and cost.
- Open toolchain only. Verilator, cocotb, Spike, Sail, riscv-arch-test, SymbiYosys, Yosys, nextpnr, OpenROAD and LibreLane.
- Sandboxed. Rootless, network-isolated containers with pinned, reproducible tools.
chip.yaml → RTL → lint → unit sim → compliance → lockstep → formal → coverage → synth/timing → FPGA / GDS
| Target | Status |
|---|---|
| Lattice ECP5 FPGA | First milestone: spec to CoreMark on hardware |
| Sky130 / GF180 shuttles | Planned |
| IHP SG13G2 | Planned |
| Repo | Description |
|---|---|
radp |
Core platform: orchestrator, agents, tool contracts, web UI |
radp-cores |
Reference RISC-V cores produced and verified by the pipeline |
radp-evals |
Agent benchmarks and eval harness |
Project RADP is in early development. Feedback from RTL, verification and physical design engineers is especially welcome.
- Read the design notes and progress on the blog
- Open an issue or start a discussion in the main repo
- Contributions are licensed under Apache-2.0 and require a CLA
Project RADP is an independent open-source project. RISC-V is a trademark of RISC-V International.
